In some applications, it may be desirable to selectively provide a highly doped Group IV-Sn semiconductor material, such as, for example, SiSn, SiGeSn or GeSn, on semiconductor surfaces without providing the same on insulating surfaces. For example, complementary metal-oxide-semiconductor (CMOS) transistors may be fabricated using methods that provide mono-crystalline semiconductor films only on the active areas of the transistors (e.g., source/drain structures). Other examples are possible as well.
Typically, the dopants in the group IV-Sn semiconductor material are provided by means of implantation of the dopants in this material. For example, Boron implantation in GeSn is described by B. Vincent et al. in “Characterization of GeSn materials for future Ge pMOSFETs source/drain stressors,” Microelectronic Engineering 88 (2011) 342-346. This approach, however, is difficult for shallow junctions. Moreover, after implantation, an anneal step is required to activate the dopants. For GeSn, the thermal budget of this anneal step is limited to temperatures below 600° C. in order to avoid Sn precipitation. This low temperature thermal budget then limits the Boron activation.